More efficient EW design
A key evolution in HPEC design is the balancing of CPU power with I/O bandwidth to increase overall performance. Traditional HPECs have featured excellent CPU power based on continually increasing computing performance, but I/O bandwidth has not always kept up with processor performance, causing potential bottlenecks and performance issues.
A balanced HPEC approach is the Kontron StarVX: It enables ease of development because it is based on only nonproprietary technology such as x86, Linux, TCP/IP, and PCIe, which eliminates niche-based deployments and reduces obsolescence risk. It delivers the I/O bandwidth and IP sockets EW application designers need in order to successfully use mainstream IT servers and deploy the system unmodified.
Additionally, Kontron’s VxFabric API technology provides a TCP/IP protocol over the PCIe infrastructure towards the application to help accelerate the design process. Its 10 GbE switch and a PCIe switch can be complemented with two single star data planes for 10 GbE and for PCIe, respectively. Designers are able to use this API with TCP/IP sockets that enable multicore computing node architectures that permit high-speed socket-based communication between blades using multiple switched-fabric interconnects within the backplane.