Xilinx Extends SmartConnect Technology to Deliver 20 – 30% Breakthrough in Performance for 16nm UltraScale+ Devices


    Now available in the Vivado Design Suite 2016.1, SmartConnect technology solves the system interconnect bottlenecks for high performance, multi-million system logic cell designs

    Xilinx, Inc. (NASDAQ:XLNX) today announced the 2016.1 release of the Vivado® Design SuiteHLx Editions, with extensions to the Smart Connect technology, delivering unprecedented levels of performance for the UltraScale™ and UltraScale+ device portfolios. In the 2016.1 release, Vivado Design Suite includes extensions to the Smart Connect technology, solving the system interconnect bottlenecks on high density, multi-million system logic cell designs. As a result, both UltraScale and UltraScale+ device portfolios now deliver an additional 20-30% performance at high utilization.

    The Xilinx UltraScale+ portfolio is the only FinFET based programmable in the industry. It includes Zynq®, Kintex®, and Virtex® UltraScale+ devices, technology available and delivers 2-5X performance/watt improvement over 28nm offerings, enabling market-leading applications such as 5G wireless, software-defined networks and next-generation advanced driver-assistance systems.

    The Xilinx Smart Connect technology includes a system interconnect IP, as well as new optimizations enabled by the UltraScale+ silicon innovations:

    • The AXI Smart Connect IP: Xilinx’s new system connectivity generator, integrating peripherals to the user design. Smart Connect creates a custom interconnect that best matches the user’s system performance requirements, thereby achieving higher system throughput at a lower area and power footprint. The AXI Smart Connect IP is available in Early Access via Vivado IP Integrator in the 2016.1 release of the Vivado Design Suite.
    • Time borrowing and useful skew optimization:These optimizations areenabled by the new UltraScale+ fine-grain clock delay insertion capability. These fully automated featuresmitigate large wire delays and deliverdesigns running at higher clock frequencies,by shifting available timing slack from the fastest paths to the critical paths of the design.
    • Pipeline analysis and retiming:These techniques allows designers to further increase performance, by adding extra pipeline stages in the design and applying automatic register retiming optimization.

    Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs, and 3D ICs. Xilinx uniquely enables applications that are both software defined and hardware optimized – powering industry advancements in Cloud Computing, SDN/NFV, Video/Vision, Industrial IoT, and 5G Wireless. For more information, visit

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