Microchip’s dsPIC33EP ‘GS’ Devices

Aids to Improve Loop Gain Performance in Digital Power Supplies

Alex Dumais, Pr. Applications Engineer, Microchip Technology Inc.

With the consistent push for higher performance and higher power density power supplies, switching frequencies are rising, which is causing digital controllers to adapt to market trends. Microchip’s dsPIC33EP ‘GS’ series of Digital Signal Controllers aimed for power supply applications is one primary example. These devices have introduced new features that reduce the execution time of the linear difference equation (LDE) and reduce overall system delays. These features help achieve higher sampling rates of the control loop(s) and mitigate phase erosion, thereby leading to improved loop gain performance.

In a digital power supply unit (PSU) there are several factors that impact loop gain performance that are specific to the microcontroller. These factors include maximum sampling rate, time required to execute compensator algorithm(s), sampling/conversion time of analog to digital converter (ADC), and microcontroller operating speed. For peak current mode control converters, the speed of the comparator and the accuracy/speed of the control digital to analog converter (DAC) will also have an impact on the PSU loop gain performance. All of these items need to be considered when selecting a microcontroller for a given application. Let’s take a look at how Microchip’s dsPIC33EP ‘GS’ devices can help improve loop gain performance for the next generation of power supplies.

The most noticeable feature of the new dsPIC33EP devices is the increase in operation frequency. The operating frequency of the new dsPIC33EP devices has increased to 70MHz, which is a maximum increase of 20 million instructions per second (MIPS) over the existing dsPIC33FJ devices. If we take a control loop that executes at a rate of 250kHz and is 60 instructions, this consumes a total of 15MIPS or 30% of the available resources on the dsPIC33FJ devices. This same control loop code consumes only 20% of the available CPU resources on the new dsPIC33EP processor when executed at the same sampling frequency. If the same percentage of MIPS is consumed after migrating to the new dsPIC33EP devices then this allows the control loop to be executed at a rate of 350kHz. Further analysis shows that phase erosion is reduced by 29% at a given crossover frequency. See Figure 1 for calculation of phase erosion due to sampling vs. cross over frequency.

Figure 1: Phase Erosion due to Sampling

In most PSUs that employ a digital compensator, the control of the power stage is typically governed by a simple LDE.  While the LDE approach is well known and commonly used, digital implementations are conducive to implementing nonlinear control algorithms. Nonlinear techniques, however, are beyond the scope of this article.