We expect a new set of standards to be developed to govern Internet of Things safety

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Cadence Design Systems is a leading provider of EDA and semiconductor IP. Its custom/analog tools help engineers design the transistors, standard cells, and IP blocks that make up SoCs. Steve Lewis, a bachelor in electrical engineering with an emphasis in analog design from Santa Clara University is Product Marketing Director, CIC and Packaging Group at Cadence. He talks extensively on new Virtuoso ADE as how does it provide analog designers with an integrated verification methodology that eliminates any guess work related to the status of the overall design progress. He also went on elaborating on the specific benefits to automotive, medical and IoT designers. For the last 10 years, Steve has been responsible for both the Virtuoso Schematic Editor and the Virtuoso Analog Design Environment product lines.

ELE Times: What are the key highlights of Virtuoso solutions? Do they address the challenges designers face today?
Steve Lewis: With the delivery of the Cadence next-generation Virtuoso platform, the new Virtuoso Analog Design Environment (ADE) product suite has been designed to be more task-specific for analog, custom and radio-frequency (RF) design, the enhanced Virtuoso Layout Suite includes significant improvements in usability and performance.

The main tenet of the new Virtuoso ADE is to provide analog designers with an integrated verification methodology that eliminates any guess work related to the status of the overall design progress. Additionally, having a single dashboard that is a single repository for all of the design’s architectural specs linked to the individual tests is designed to confirm that those specs are being met and can reduce the risk of missing something being tested, because, previously, it was being tracked outside of the Virtuoso framework.

ET: How does Virtuoso improve performance 10x and capacity improvements?
Steve Lewis: The benefit comes both from performance and usability improvements.  In terms of performance, new rendering engines have been developed to significantly improve the display of large and dense layouts. Layout designers tend to focus on small areas of the design and then pan or zoom appropriately to continue their work.  In the past, that could be frustrating when working with particularly large or dense renderings of the layout previously took a long time to redraw. That is no longer the case. Now layout designers can work using their preferred methods with their preferred visibility level and get their job done.

With respect to usability, two areas were improved: Module Generators (ModGens) and routing. ModGens provide an automated way to quickly create an array of devices, properly spaced and inter-digitated based upon the design rule check (DRC) rules of the technology. Customers can now take advantage of the automated process but can also easily make surgical changes interactively without having to regenerate the array.

In the area of routing, improvements in the specific pin-to-trunk routing style provide automation to help properly size the trunk route to carry the desired current without creating an electro-migration (EM) violation and to tap off lines to specific pins that will be DRC-correct.

ET: What are the new industry standards that Virtuoso will address?
Steve Lewis: The standards are not so much new as they are emerging. International Organization for Standardization (ISO) standards for medical, automotive, industrial, aviation, etc. have been emerging for the last few years. We expect a new set of standards to be developed to govern Internet of Things (IoT) safety. These standards always prescribe a list of tests that must be validated in order for the device (block, chip, board, etc.) to be declared ISO-certified. The ability to show that you have tested against each of these industry specifications (and probably more to be on the safe side) is the central tenet. That’s how Virtuoso helps.

ET: Can you elaborate on the specific benefits to automotive, medical and IoT designers?
Steve Lewis: When designing for a standard, the operator must be able to show or “trace” that they have not only fully tested the design in a prescribed way, but the designer must also show when it was tested, who tested it, what the results were, where is the data archived, what tools were used, etc.

The Virtuoso tools make that process easy, and because the platform is integrated into the working world (as opposed to being tracked outside), there isn’t a risk of a test becoming out of date, or accidently missing testing a block within the design.  From the Virtuoso tool suite, you can produce the information that you need to show (and would need to demonstrate later if there is a question) to the certification board.

ET: Please explain how Virtuoso helps in Analog device traceability?
Steve Lewis: Cadence’s recognized leadership in the analog domain made us the most likely vendor to be able to bring the ability to properly trace and manage analog designs properly for ISO certification. While the digital domain has provided its designers with the ability to trace its designs and develop coverage metrics, the analog domain was rather ad hoc. Designers now can use a “familiar” feeling user interface (UI) to trace what they are doing and provide the proper reports—all while not having to completely upend their tried and true design methodologies that they have established over the years within the Virtuoso ADE suite of tools. The Virtuoso ADE Verifier works behind the scenes to gather up the proper information and displays the current design status in an easy to read dashboard-like setting. Now test failures are easy to find and track back to their origin, facilitating the ability to quickly make corrections. Only a fully integrated methodology like ours allows for this kind of quick find and fixes methodology.

ET:  What improvement you have noticed in India during the last six month in the overall ecosystem in ESDM sector?
Steve Lewis: With campaigns like Make in India and Digital India, the Indian government has introduced several initiatives over the last year and a half to provide an impetus to the nascent electronics industry. These initiatives have provided local companies with opportunities to design products for the domestic market. Apart from providing financial support to the local electronics system design and manufacturing (ESDM) ecosystem, the government has also given in-principal approval to set up 28 electronic manufacturing clusters as well as common facility centres (CFCs) across the country. Multiple states have broken ground or announced an intent to set up the same including Andhra Pradesh and Chhattisgarh.

With government support to ESDM entrepreneurs and startups, and the huge demand for electronics in the domestic market, we are hopeful of seeing the ESDM ecosystem pick up and thrive in India.

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