SiFive and Open-Silicon Host the final RISC-V Tech Symposium 2018 in New Delhi

SiFive and Open-Silicon, two global giants of the semiconductor industry concluded their six city RISC-V Tech Symposium Tour in the capital city. The Symposiums started in Hyderabad and were also conducted in Bangalore, Chennai, Pune and Kolkata. The event was attended by academic leaders and dignitaries such as Naresh Rana, Manager of Business Development, Western Digital,  Pankaj Kakkar, Solutions Group Director, Cadence, Smruti Ranjan Sarangi, Associate Professor, CSE, IIT Delhi, Kunal Ghosh, Director & Co-Founder, VSD, Anagha Ghosh, Business Head & Co-Founder, VSD, Swamy Irrinki, Sr. Director of Marketing, ,  SiFive , Dr. Shafy Eltoukhy, SVP of Operations and GM of SoC Division, SiFive and Huzefa Cutlerywala, MD of Open-Silicon India.

The events were hosted to spread awareness for RISC-V, an open instruction set architecture that has stirred a revolution in the industry and is rapidly increasing its ecosystem. It is being preferred by leading system, chip design organizations, several start-ups and governments around the world.

The tech symposium in New Delhi enabled industry experts, students and engineers to share their thoughts on RISC-V ecosystem and understand the role of RISC-V to develop indigenous processors for control and security by national Government, and current research being conducted at Indian educational institutes and research organizations. The esteemed speakers used the platform to discuss the nuances of Hardware Designing and Designing complex RISC -V SoCs.

The six-city tour saw around 1250+ students, industry experts, engineers and researchers gather and share the platform with the esteemed speakers. During the tour, SiFive also announced first of its kind Design Contest in India. The Design Contest aims to enable some of the most underutilized ideas from Indian non-commercial entities, including academic institutions, students, research groups, non-profits or individuals. SiFive will collaborate with the best ideas and provide the winners’ access to custom CPU IP, design support, and help delivering working samples for the chip. The contest will run from 21st August till 30th November 2018.

“The fact that this open architecture has the capacity to bring custom silicon to all inventors and makers will benefit the entire semiconductor ecosystem,” said Shafy Eltoukhy, SVP of Operations and GM of SoC Division, SiFive. “We are already witnessing a major shift in innovation from thinkers and dreamers who were previously unable to access custom silicon”, he added.

Previous articleDiscoms propose tariff for electronic vehicles
Next articleFree Embedded Software for Enhanced LoRaWAN gets New Update
ELE Times provides a comprehensive global coverage of Electronics, Technology and the Market. In addition to providing in depth articles, ELE Times attracts the industry’s largest, qualified and highly engaged audiences, who appreciate our timely, relevant content and popular formats. ELE Times helps you build awareness, drive traffic, communicate your offerings to right audience, generate leads and sell your products better.