All Digital Phase-Locked Loop Combines sub-mW power consumption, small size and industrial-grade performance
At the 2017 International Solid-State Circuits Conference in San Francisco (US), imec, the world-leading research and innovation hub in nano-electronics and digital technologies, Holst Centre (set up by imec and TNO) and ROHM on February 8, 2017, presented an all-digital phase-locked loop (ADPLL) for Internet-of-Things (IoT) radio transceivers. Whereas a PLL is traditionally one of the major power consumers in a radio and can take up to 30% of the radio area, this new ADPLL features a small area (0.18mm² in 40nm CMOS), low power consumption (0.67mW) and excellent performance. With all spurs lower than -56dBc and jitter below 2ps, which is beyond state-of-the-art digital PLLs, the new ADPLL shows an excellent robustness.
The intuitive IoT relies on tiny sensor nodes, invisibly embedded in our environment and wirelessly connected to the internet. As billions of IoT devices are set to be deployed, battery replacement becomes impossible and therefore, power consumption reduction, especially in wireless connectivity, is one of the leading concerns and challenges on low power radio design to address.
The PLL is the radio component for frequency synthesis and has traditionally been an analog component, although the research community has been working on digital alternatives. All-digital PLLs enable a smaller footprint, better control and testability, and improved scaling to advanced CMOS nodes. However, to-date, they have lagged behind in terms of performance, compared to analog solutions.