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    Mentor provides EDA tools to design complete electronic systems

    Mentor Graphics provides EDA tools to design complete electronic systems, from the chip’s packaging, to printed circuit boards, to multiple boards integrated with connectors and cables, to systems of systems such as automobiles and factory equipment, integrating increasingly with mechanical/mechatronic tools to create smart cars, smart factories and even smart cities. Harry Foster, Chief Scientist Verification, Mentor Graphics in an interview with Pratibha Rawat, Sub Editor, ELE Times, discusses and gave the insight on EDA tools and solutions to design engineers. Excerpts.

    ELE Times: What is the latest EDA tool your company is offering focusing on IC Design and how is it different from its predecessors?
    Harry Foster: The latest product launch from Mentor Graphics is for the Veloce Strato emulation platform, Mentor’s third-generation emulation platform with a capacity roadmap to 15 billion gates. In addition to announcing the VeloceStrato platform, Mentor announced two significant products that are part of the platform: the Veloce StratoM high-capacity emulator, and the Veloce Strato OS enterprise-level operating system. Veloce StratoM is the initial piece of hardware for the Veloce Strato emulation platform, and Veloce Strato OS is the centerpiece of the total emulation system as it allows verification teams to take full advantage of the power of the Veloce StratoM hardware.

    For those who are not familiar with hardware emulation, let’s talk about howhardware emulation works. A hardware emulator is a high-capacity, piece of hardware equipment that is designed to verify SoC designs using the RTL description of the SoC design. The RTL description is a ‘software or code’ version of the design. But when it is compiled on to the emulator (which is loaded with boards that are populated with chips)it becomes a hardware version of the design that is resident in the emulator. From that point engineers run ‘tests’ on the hardware version of the designto verify that the design works as expected. In addition, they can run firmware, OS boot code and many other ‘application’ types of software on the hardware version of the design to verify that the software for the system works in advance of actual silicon availability. An emulation team uses the test results to debug the hardware design and the software that is targeted for the design.

    Mentor Graphics is a leader in the emulation market segment and our newly released Veloce StratoM is the industry’s most advanced and scalable emulator. It enables design teams to verify design that are extremely large, in fact, up to 15-billion gates in size. While there are no designs that large today, Mentor projects that designs of this size will be a reality by 2021. The Veloce StratoM has the industry’s fastest compile-runtime-debug sequence, called throughput (5x faster than the previous generation), 10X faster time-to-visibility, or time to debug, 3X faster compilation time (with 100% success rate) and 3X faster virtual co-model bandwidth (the fastest virtual co-model solution available). All of these improvements in performance are attributed to the new Veloce Strato OS.

    ELE Times: What is your company doing to eliminate the dilemma in terms of cost for design engineers who needs entry-level desktop solutions that are fast to pick up but limited in capability?
    Harry Foster: Concerning cost in general, the EDA industry has done a remarkable job of managing cost to keep up with Moore’s Law. In fact, what is amazing is that the EDA cost per transistor continues to decrease at about 30 percent per year since 1985. This is essentially the same rate as the decrease in revenue per transistor, which is another way of stating Moore’s Law. The point is that if the EDA cost per transistor didn’t decrease at the same rate as the revenue per transistor, then we would not be able to achieve Moore’s Law.

    Obviously, there are a wide variety of EDA tools available today. Generally you will find that FPGA and PCB tools are relatively less expensive than IC design tools, and PCB and FPGA tools vary greatly as to price point and ease of use. But when you start talking about IC design tools, you have to consider not only the “cost” of the tool, but the value of what you are getting for the cost and increased productivity. Designing ICs, especially for the latest silicon process geometries, is a highly complex set of tasks that have to be performed by highly skilled engineers. There are many complex tasks and tools that make up the IC design process so they are not inexpensive relative to other forms of software like Microsoft Word or Excel, but the cost is more than worth it if companies are able to deliver a working chip to market before competitors and thus maximize profitability.

    Nonetheless, we are value sensitive to our customers. As an example, for PCB systems design, Mentor Graphics offers a portfolio that scales based on design and organizational complexity. Small teams need tools that are easy to adopt and use. Large teams made up of domain specialists need a collaboration infrastructure including IP management. Design complexity does not scale equally with organizational complexity (small teams can design complex products), so we provide solutions for that middle ground as well.

    ELE Times: What are the main key points IC Design engineers should look for in an EDA tool before buying?
    Harry Foster: The success of the electronics industry has been grounded in both EDA innovation and automation. But equally important in the successful adoption of advanced EDA tools is robustness and quality in the generated results. Tools that do a second-rate job can actually miss errors or potentially identify errors that really aren’t there (false positives). In the case of false positives, you can waste a significant amount of time trying to find an error that doesn’t actually exist. And if you actually have a design that has an error, and it doesn’t get detected before you send it to manufacturing, it can lead to chips needing to be re-spun. This can lead to market delays and depending on the market cost millions or even billions of revenue. And if an error isn’t detected until a product is out in the market, in some cases it can lead to product recalls.

    ELE Times: How different it is to develop software for manufacturing giants and for scholars and researchers?
    Harry Foster: Mentor Graphics EDA tools and solutions have been successfully adopted by both industry and academia, and we see no difference in the way we develop our tools for our various stakeholders. Both industry and academia are very important to us. In fact, we actively participate in both academia and industry educational programs and partnerships to help train the next generation of innovators. Through our company’s Higher Education Program, Mentor Graphics strives to develop long term relationships with engineering colleges and universities around the world. For example, Mentor Graphics has partnered with more than 1200 colleges and universities worldwide. The program provides: access to millions of dollars’ worth of Mentor Graphics software for a minimal customer support fee; free access to regular customer training for all faculty/staff in the department; and access to technical support services for faculty and staff of the department.These partnerships are mutually beneficial as their research helps us better foresee what design challenges are on the horizon and proactively develop technologies to overcome those challenges.

    ELE Times: Can EDA technology for designing integrated circuits be applied to the design of systems? Kindly tell us something in this perspective.
    Harry Foster: The term “system design” or what actually constitutes a system is ever evolving with increasing degrees of integration and minimizations. Today, thanks to EDA technology and silicon process miniaturization, you can integrate essentially the compute power of entire electronic system into a single chip; consisting of multiple processors, digital logic, analog, mixed-signal, and often radio-frequency functions.

    To address this evolution (and revolution) in complex design, Mentor Graphics provides EDA tools to design complete electronic systems, from the chip’s packaging, to printed circuit boards, to multiple boards integrated with connectors and cables, to systems of systems such as automobiles and factory equipment, integrating increasingly with mechanical/mechatronic tools to create smart cars, smart factories and even smart cities. Mentor Graphics also offers embedded software development tools. Software is of course becoming a greater component of modern systems, especially emerging IoT devices and advanced automotive designs.

    ELE Times: Growing introduction of Internet of Things (IoT) devices tell us something about design verification challenges? Kindly provide a brief introduction to “Portable Stimulus”
    Harry Foster: During the past decade or so, the electronics industry has done a remarkable job of adopting new advanced verification technologies to address rising design complexity. For example, the introduction of constrained-random simulation helped verification engineers generate several orders of magnitude more stimulus using automation versus hand-written directed test. The introduction of commercial verification IP provided engineers more-efficient ways to interact with complex interface protocols. The UVM standard brought reuse methodology to verification environments, both in terms of infrastructure and best practices. However, while these techniques have done wonders to improve block- and subsystem-level verification, they have not scaled effectively (nor productively) to the SoC, full chip or system-level verification process, nor will they do so in the future.

    A new way of thinking about verification is essential to productively and effectively verify today’s designs. What is required for SoC verification is the ability to generate system-level use-case test scenarios. These scenarios often require software running on an embedded processor that must be synchronized with interface stimulus and events. Scenario-based testing is difficult to achieve using existing verification approaches (such as UVM). In addition, today’s verification engineers want to describe the intent of a given test, and then let automation generate the low-level details for the appropriate test scenario. Finally, today’s verification engineers want to describe the intent of a test once, and then allow automation to retarget the test across different verification engines (e.g., simulation or emulation or prototyping). The Accellera Portable Stimulus Standard is currently being developed to meet these goals, and Mentor Graphics is activity involved. In fact, Mentor Graphics has been a leading researching in graph-based portable stimulus for many years. For example, our Questa in Fact solution is the industry’s most advanced Portable Stimulus test bench automation solution.

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