Mouser Left Banner
Mouser Left Banner
Mouser Left Banner
Mouser Right Banner
Mouser Right Banner
Mouser Right Banner

    Industry’s First PCIe 7.0 IP Solution for Next-Gen HPC and AI Chips Designs

    Synopsys recently unveiled the industry’s first complete PCIe 7.0 IP solution, designed to accelerate trillion-parameter HPC and AI supercomputing chip designs. This new IP solution future-proofs bandwidth for hyperscale AI data centre infrastructure, addressing the demanding requirements of transferring massive amounts of data for compute-intensive AI workloads.

    Key Highlights of Synopsys’ PCIe 7.0 IP Solution

    1. Complete Solution: Synopsys offers the industry’s only complete PCIe 7.0 IP solution, including the controller, IDE security module, PHY, and verification IP. This solution enables data transfers of up to 512 GB/s bidirectional in an x16 configuration.
    2. Power Efficiency and Low Latency: The pre-verified PCIe 7.0 Controller and PHY IP provide low latency data transfers and up to 50% more power efficiency compared to prior versions while maintaining signal integrity.
    3. Security: The Synopsys IDE Security Module for PCIe 7.0, pre-verified with the Controller IP, offers data confidentiality, integrity, and replay protection against malicious attacks, ensuring a secure data transfer environment.
    4. Experience and Reliability: With more than two decades of PCIe IP experience and over 3,000 design wins, Synopsys offers a low-risk path to silicon success, providing customers with a robust and reliable IP solution.

    This solution is crucial for chip makers addressing the bandwidth and latency challenges posed by large language models and compute-intensive AI workloads. Synopsys’ PCIe 7.0 IP solution supports secure data transfers, mitigating AI workload data bottlenecks and enabling seamless interoperability within the ecosystem.

    At the PCI-SIG DevCon in Santa Clara, Synopsys demonstrated the world’s first PCIe 7.0 IP over optics, showcasing the technology’s capabilities in real-world scenarios. This includes Synopsys PCI Express 7.0 PHY IP electrical-optical-electrical (E-O-E) TX to RX running at 128 Gb/s with OpenLight’s Photonic IC, and successful root complex to endpoint connection with FLIT transfer using Synopsys PCIe 7.0 Controller IP.

    Synopsys’ PCIe 7.0 IP solution is part of a broader portfolio for high-performance computing (HPC) SoC designs, including solutions for 1.6T/800G Ethernet, CXL, and HBM. The company’s extensive interoperability testing, comprehensive technical support, and robust IP performance help designers accelerate time to silicon success and production.

    Industry leaders such as Intel, Astera Labs, Enfabrica, Kandou, XConn, Rivos, and Microchip have embraced PCIe 7.0 for AI data center infrastructure, recognizing its importance in delivering high-bandwidth, low-latency connectivity critical for data-intensive and latency-sensitive workloads.

    Overall, Synopsys’ PCIe 7.0 IP solution represents a significant advancement in enabling next-generation HPC and AI chip designs, providing a secure, efficient, and high-performance interconnect solution for the evolving demands of hyperscale AI data centers.

    Rashi Bajpai
    Rashi Bajpai
    Rashi Bajpai is a Sub-Editor associated with ELE Times. She is an engineer with a specialization in Computer Science and Application. She focuses deeply on the new facets of artificial intelligence and other emerging technologies. Her passion for science, writing, and research brings fresh insights into her articles and updates on technology and innovation.

    Technology Articles

    Popular Posts

    Latest News

    Must Read

    ELE Times Top 10