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    Emergence of Design and Simulation tools – “Turnaround Time and Cost of Traditional Trial and Error Iterations”

    Texas Instruments provide a wide variety of design tools, models and simulators to help you with the board design process. Their portfolio helps you select the right IC, design the application BOM, analyze your design and even export it to your favorite CAD environment. To verify your design, they offer the Pspice for TI design and simulation tool that includes an extensive library of simulation models for products.

    Design and Simulation tools being the heart of design engineers, we can’t miss upon this. Our ELE Times Sub Editor and correspondent Sheeba Chauhan took this opportunity to conduct a very candid and insightful interview with Guha Lakshmanan, Design Verification Engineer, Texas Instruments India.



    Guha Lakshmanan, Design Verification Engineer, Texas Instruments India

    ELE Times: How are design and Simulation tools supporting high-frequency electronic designs?

    Guha Lakshmanan: High Frequency Electronic designs present several challenges during the front-end development phase of Analog and Mixed Signal (AMS) design, verification and layout. While design challenges are met through innovative circuit design techniques, verification and layout challenges are heavily dependent on simulation tools. For AMS simulations, performance is the key concern. Differential Algebraic Equations (DAE) solvers used in conventional analog circuit simulators are inherently slow. On the other hand, Event-Based solvers, used by digital simulators, cannot accurately model the continuous time-space of analog circuits. While modeling in mixed-signal languages such as VHDL-AMS and Verilog-AMS have resulted in improved simulation speed, breaking free from DAE solvers and moving into purely digital simulations through behavioral and performance modeling for analog IPs, with the level accuracy acceptable to ensure quality is the breakthrough that is most anticipated.

    TI’s analog DV experts explore and innovate cutting-edge methodologies that leverage the latest development in IEEE standards such as System.

    Verilog User Defined Net types (UDN)  for modeling current and voltages and its loading effects in discrete-time digital simulations as was only possible with purely analog modeling languages such as Verilog-A. A deep understanding of the risks and limitations of these modeling techniques is very important to secure the ultimate goal of high-quality silicon. Speed of simulations will always come with a certain degree of compromise in accuracy. By carefully selecting the stage of design where such modeling is used and later closing the design phase with comprehensive schematic simulation before PG ensures the dual objective of increased design throughput and excellent design quality.

    Likewise, there are several more exciting developments in high speed mixed signal layout such as estimation of EMIR and Dynamic IR drop. Further, ML aided simulations are now becoming increasingly common offering significant promise of improved simulation performance. With faster and denser AMS designs, these methodology improvements are pivotal to meeting TTM demands of high-speed designs.

    ELE Times: As opposed to trial-and-error, a smart simulation process allows targeted implementation of design choices in various stages of the development cycle. How are design and Simulation tools reducing the risk factor of error in the development process? 

    Guha Lakshmanan: Yes, many trial-and-error iterations can be quite costly and can become an impediment to timely entry to market, due to complexity, long turnaround times and costs involved in hardware prototyping.  Advanced and more accurate modeling of low-level details sufficient for circuit level analysis coupled with faster and accurate device, circuit and system level simulation-based analysis tools helps in advancing the trial-and-error analysis to the design stage.  Due to the emergence of design automation tools tightly coupled with underlying component models, analysis and simulation tools, several what-if analysis and architectural decision making can benefit from more accurate analytical backing.  In the absence of this it involves much more manually intensive, iterative and error-prone processes.

    Multiple process milestones are integrated into the simulation and design tools. To name a few, metric driven verification management tools for tracking what was planned to be verified with what was actually done; coverage management tools for tracking the items in the plan using embedded coverage and automated coverage items to quantify the items in the plans are indeed covered; linters – C code linting tools to enable checking of coding guidelines adherence (that ensure conformity to correct by construction coding style and rules); integrated code development environments – these enable coding of the stimulus that are better viewed and are in sync with the right sub-functions and packages; methodology – methodologies like Universal Verification Methodology (UVM), Portable Stimulus Standard (PSS) enable re-use of proven code so that the error in re-learning is avoided.

    ELE Times: What are the latest design tools developed recently and for what application?

    Guha Lakshmanan: There are emerging ML based analog design, verification and layout tools that are showing a lot of promise. All EDA vendors have recently unveiled ML powered tools for various aspects of analog design and development. For example, I liked a vendor tool that promises to improve monte carlo and PVT simulation time and accuracy for analog IPs. While it may still be a few years away before these tools can claim maturity, there is significant current research and emerging wider application of machine learning (ML) and artificial intelligence (AI) in the areas of more accurate component modeling, component development, circuit and system design (including analysis, synthesis and optimization), verification and test.  I predict that all commercial EDA vendors will focus on increased use of AI and ML techniques in their tool offerings, if not already.

    ELE Times: Design and Simulation tools are making work life easy for professionals by testing an alternative plan/design without evaluating on a real system which is costly and time consuming.  What is your opinion on the potential benefits of these tools?

    Guha Lakshmanan: Yes, absolutely. Due to the emergence of design automation and simulation tools, more complex, iterative and manually involved analysis can now be performed with the help of computing machines in a short time.  This helps reduce the development time by several orders of magnitude and can be looked upon as making work life easy for professionals.  However, the trend has been quite different to compress more in shorter time, address solutions for more complex problems, and systems that can do more in less area with lower power and time, all due to competitive market pressure, which is now in the realm of possibility to be addressed with the help of advanced design automation tools. Another perspective is the impact of supplemental productivity from project management and planning tools is also constantly raising the bar of productivity.

    ELE Times: Tell us more about recent tools and upcoming technology in design and simulation?

    Guha Lakshmanan:  There are a lot of new offerings from all major EDA vendors who are quickly adapting to the high demands of the semiconductor design and development market. Staying true to the cliched Moore’s law, the industry is constantly demanding a lot more development in less time and resources. As a result, in every phase of design and development, EDA improvements are conspicuous. Sponsored technical symposiums are the place to witness and appreciate these developments where the vendors showcase their most recent tools and technologies. My personal favorites are the tools that apply and leverage machine learning (ML) and artificial intelligence (AI) in design, verification and test to make sense of and benefit from deluge of data.

    Sheeba Chauhan | Sub Editor | ELE Times

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