Toshiba’s Spur Canceled Clock Generator receives sensitivity in Wireless SoCs

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Toshiba has developed a spur canceled clock generator (SCCG) that recovers receiver sensitivity of wireless connectivity IC.

The SCCG recovers receiver sensitivity by suppressing the spur, interference that originates from the clock signal, and achieves receiver sensitivity of -93 dBm for all channels in Bluetooth Smart ICs.

Recent wireless connectivity ICs integrate analog blocks, such as RF circuits, digital blocks, and mixed signal blocks, such as AD converters, on one chip.

However, some of the harmonics of the reference clock signal for AD converters and digital circuits, known as clock spurs, degrade receiver sensitivity.

Conventional techniques to recover sensitivity have resulted in issues with additional power consumption, chip size and development costs.

Toshiba’s solution is a clock generator that suppresses spur by delaying some parts of the clock.

This clock delay generates two kinds of clock spurs that have reverse phase with the same amplitude, which cancel each other out. Since the generator’s power consumption is 18μW and the size is 40μm×120μm, clock spur is suppressed without any increase in power consumption or size.

This approach recovers 4dB of sensitivity degraded by the spur, and applied to Bluetooth Smart IC achieves -93dBm receiver sensitivity.

The spread of such applications as wearable devices is boosting demand for wireless connectivity ICs. Toshiba will proactively continue to expand its line-up of high performance wireless ICs, and plans to launch a Bluetooth® Smart IC with the SCCG this summer.

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