RISC-V open ISA can help aerospace and defense designers who are facing challenges of minimizing power consumption, BOM cost and board area by allowing the optimization of the instruction set to give the most efficient implementation for each specific application.
The field of aerospace and defense design is extremely broad in scope, encompassing hand-held, portable, vehicle-mounted, maritime, airborne and space; manned and unmanned systems, for tactical or strategic applications. Aerospace and defense designs have many things in common, such as the need for high reliability in harsh environments during critical missions, yet each type of system presents its own unique challenges.
Designers may need to contend with tough power constraints for portable systems, or severe thermal constraints for systems located in equipment subjected to high temperatures or without forced ventilation. The end equipment may be subjected to extreme shock or vibration, extreme temperatures, extreme levels of moisture or humidity, or extreme amounts of radiation.
Aside from environmental factors, designers of aerospace and defense systems also need to navigate supply-chain issues such as the diminishing base of suppliers who are willing to invest in achieving the high levels of qualification and certification needed for many types of aerospace and defense systems. In recent years, various government defense programs have also begun to pay increased attention to the trustworthiness of components and intellectual property (IP) designed into systems they are purchasing.
Field programmable gate arrays (FPGAs) provide designers with flexible platforms for logic integration, which can be used across the full scope of aerospace and defense designs, addressing the challenges listed above. Many defense systems depend on FPGAs for high-speed signal processing, hardware acceleration, I/O expansion and embedded processing.
The most flexible and adaptable approach to embedded processing in FPGAs makes use of soft IP processor cores. The advantage of using a soft IP core to implement a microprocessor in an FPGA is the high degree of flexibility this provides when compared to a hard-wired processor, which is permanently configured and cannot be modified by the designer.
An additional advantage of a soft IP processor core is the availability of hardware description language (HDL) code for the processor, which allows the designer or other third parties to inspect the processor IP to ensure it contains only the logic required to perform its intended function, no more and no less. This is a key tenet of both design assurance, as encountered in commercial aviation applications, and in trustworthiness, as encountered in certain defense applications.
However, such flexibility comes with a high price, as most vendors of microprocessor IP charge very large fees for delivering HDL versions of their processor IP, and almost never allow modification of the IP for purposes of optimization.
The emergence of the new RISC-V open instruction set architecture (ISA) for microprocessors has brought designers greater freedom to adjust and optimize the microarchitecture so that it optimally meets the needs of their development program. It also allows designers full inspection of HDL code for the purposes of design assurance and trust, without incurring very large charges from IP vendors.
RISC-V is an open instruction set that is available under a Berkeley Software Distribution (BSD) license. Designers may use or create any IP which implements the RISC-V instruction set, with no royalty or license payable for using the instruction set. Standard extensions to the instruction set have been frozen, meaning that software written in the future will always be able to use these standardized extensions as they exist today.
As the instruction set is open, and there is plenty of op code space left, designers may choose to extend the instruction set to suit the exact needs of their own system with their very own custom instructions. For example, if a particular sequence of instructions occurs very frequently in the code being created for a specific application, the designer can choose to create a new custom instruction to implement the frequently-used sequence.
The designer can create additional logic for the microprocessor IP to implement the new instruction quickly and efficiently. This can give a significant performance boost and reduce the code space for the executable code. Prior to the advent of RISC-V, such modifications to processor soft IP were available only to organizations holding architectural licenses, which are usually prohibitively expensive.
Many defense programs have a requirement to use electronic components and embedded IP that are sourced from trusted suppliers. There are very few products that meet this requirement. Having IP which is available for inspection in HDL form is useful in allowing the designer or the end customer to validate that the IP contains only the code needed to implement the desired function. It also assures the end customer for the equipment that the IP is safe for use in aerospace and defense systems.
Inspection of HDL code can also help achieve validation of soft IP for safety-critical applications such as commercial aviation systems, which undergo rigorous procedures for airworthiness certification.
The RISC-V ecosystem is continuously expanding. With its Mi-V initiative, Microsemi offers a comprehensive suite of tools and design resources developed internally and by numerous third parties to fully support RISC-V designs. The Mi-V ecosystem aims to increase adoption of the RISC-V ISA and Microsemi’s soft CPU product family.
RISC-V can help military and aerospace designers who are facing challenges of minimizing power consumption, BOM cost and board area by allowing the optimization of the instruction set to give the most efficient implementation for each specific application. Further, designers of aerospace and defense systems can meet requirements of inspectability with RISC-V.