Anritsu Company Introduces Software for MP1800A BERT that Generates High-speed Serial BUS Link Sequences



New Serial Data Test Software Supports Verification of LTSSM for Accurate, Efficient Evaluation of PCI Express and USB Interfaces

Anritsu Company introduces High-Speed Serial Data Test Software for its industry leading MP1800A Signal Quality Analyzer BERT. With the software installed, the MP1800A can generate high-speed serial BUS link sequences as well as conduct jitter load tests so engineers can perform highly accurate signal integrity tests for efficient evaluation of high-speed PCI Express and USB interfaces.

The High-Speed Serial Data Test Software controls the MP1800A, including its plug-in jitter modulation signal source, pulse pattern generator (PPG), and error detector (ED). The integrated solution supports Link Training and Status State Machine (LTSSM) by performing state machine control of the high-speed BUS interface. This functionality, along with the jitter tolerance test capability, results in faster, more efficient test times and more accurate signal integrity measurements on interfaces used in high-speed interconnect designs.

Three different test functions are written into the software. A Jitter Tolerance Test Function allows the MP1800A to conduct jitter tolerance tests of PHY devices with impressed SJ/RJ/BUJ. It can also conduct low-rate estimated BER measurements to verify device margin faster than alternative solutions. All jitter tolerance measurement results can be saved as an HTML or CSV report.

With the PCI Express Link Sequence Generation Function, the MP1800A BERT can control device status transitions using sequence generation that supports PCI Express Base Specification Rev. 1.0-4.0 device Logical Sub Block evaluation. 8B/10B, 128B/130B, Scramble, and SKIP insertion can be generated when the PCI Express Link Sequence Generation function is installed in the MP1800A, as well.

The High-Speed Serial Data Test Software also has a USB Link Sequence Generation Function that allows the MP1800A to generate transition to loopback for evaluating USB3.1 Gen. 1-2 devices. This function allows the BERT to generate 8B/10B, 128B/132B, Scramble, SKIP Insertion, and LFPS.

A modular BERT, the MP1800A can be custom configured to meet a variety of high-speed signal integrity applications. The plug-in PPG module supports high quality output and high amplitude signals. The ED has high input sensitivity and internal clock recovery to support signal analysis, including Bathtub and Eye Diagram measurements. Various jitter types, including SJ/RJ/BUJ, can be generated by the jitter modulation source, which supports jitter tolerance tests.

To learn more visit and follow Anritsu on FacebookGoogle+LinkedInTwitter, and YouTube.