The word packaging literally means wrapping or protecting goods. In the world of media it generally refers to the flow and sequencing of a commercial production or news from start to end. Packaging in electronics is a different term, which includes the design and production of enclosures for electronic devices ranging from individual semiconductor devices up to complete systems. Electronic packaging is a major discipline within the field so as to develop durable and long lasting functionaries.
Almost all appliances and systems in various spheres including home appliances, information, industrial, medical and transportation systems contain semiconductor chips. The Semiconductor packaging process is a standout amongst the most emergent and astoundingly approved sectors.
This worldwide market has been developing at a higher pace with the development of imaginative frameworks and a developing end-client tendency. Semiconductor packaging materials are a class of electronic solutions used to form the connection of IC chip to the package substrate.
Packaging practice and machinery
Semiconductor packaging play an important role in protecting chips from the surrounding
thereby ensuring electrical connection for chip mount on printed wiring boards. Semiconductor packaging and assembly embrace various technologies such as material, surface treatment, bonding, electromagnetic characteristics, three-dimensional (3D) chip
stacking, thermal dissipation, part integration and circuit implementation design.
Semiconductor packaging has a crucial role in manufacturing because it is among the closest steps to the end customers. However, the complexity of production conditions makes controlling a semiconductor packaging facility a challenging task, and dynamic factory simulation has been considered as an effective means to fulfil this task.
Packaging is a backend operation in semiconductor manufacturing. Compared with the frontend operations (i.e., wafer fabrication and wafer sort), the backend operations require substantially less time and expenditure. In addition, the backend operations are closer to the end customers than the frontend operations, marketing time is more critical for the backend operations.
A chip scale package is a type of integrated circuit package. In order to qualify as chip scale, the package must have an area greater than 1.2 times that of the die and it must be a single-die, direct surface mountable package. The die may be mounted on an interposer upon which pads or balls are formed like flip chip ball grid array packaging. The pads may be etched or printed directly onto the silicon wafer, resulting in a package very close to the size of the silicon die. Such a package is called a wafer-level package (WLP) or a wafer-level chip-scale package.
Wafer-Level Packaging (WLP) Technology
The manufacturing processes depends on the requirements that the users must meet to ensure reliability of the end product. Integrated circuits are designed to provide all the electrical functions needed and to fit into a specific set of packages. The bond pads on the chip are connected to the pins of a conventional package through wire bonding. Design rules for conventional packages require the bond pads to be located at the perimeter of a chip. To avoid two designs for the same chip, a redistribution layer is generally required to connect bumps to bond pads.
Dual in-line package
A dual in-line package is an electronic component package with a rectangular housing and two parallel rows of electrical connecting pins. The package may be through-hole mounted to a printed circuit board (PCB). Increasingly complex circuits required more signal and power supply leads. Eventually microprocessors and similar complex devices required more leads than could be put on a DIP package, leading to development of higher-density chip carriers. Furthermore, square and rectangular packages made it easier to route printed-circuit traces beneath the packages.
The semiconductor packaging technology has grown dramatically and several thousands of different semiconductor package types have been made. Industries such as aerospace, healthcare, data centres and many other industries are expected to be the key growth drivers for the advanced semiconductor packaging market in the upcoming years. Considering the market apprehensions, several semiconductor companies worldwide have developed different modes of operation in order to meet the industry demands. Here is a list of some of the top semiconductor companies and their status in manufacturing.
Toshiba has developed a broad range of products, including a package for large-capacity memory, a thermally enhanced small and lightweight IC, a sensing device designed for the Internet of Things (IoT), and other innovative products. These packages are contributing to the enhancement of performance and downsizing of electronic devices according to their applications. Toshiba has developed a mass-production technology with an EMI-shielding film on the surface, referred to as EMI-shielded packages, using a sputter deposition process capable of forming a metal thin film more stably compared with the screen printing process using a metal paste. Newly developed special tools are incorporated into the sputtering equipment generally used for the front-end process, so as to prevent overflow of the shielding film to the backside of the package without the need for costly protective tape.
Based on a decades-long tradition of excellence in R&D, the advanced packaging solutions also leverage the scale of company’s manufacturing infrastructure, and is developed in close collaboration with design and operation partners. With packaging development, the company is well poised to deliver the next wave of innovative solutions that meet customer needs today and in years to come.
The innovative approach to packaging helps customers differentiate their products through advancements that deliver reduced package sizes, enhanced reliability, and increased performance in areas including power density, isolation, and signal integrity. It also includes thousands of diversified lead-free packaging configurations that range from traditional ceramic and leaded options, to advanced chip scale packages using fine pitch wire bond and flip chip interconnects.
SK hynix has invested in the construction of NAND Flash memory chip packaging and testing production line, responsible for semiconductor post processing services including the construction of chip packaging, testing, modules and other production lines. At present, the packaging and testing are carried out in the first phase of the project. After the completion of the second phase, the first phase of the project will focus on the testing , while the second phase will focus on the packaging process.
Taiwan Semiconductor Industry
Companies in Taiwan are engaged separately in each process of manufacturing of semiconductor from chip designing to its fabrication. From wafer to packaging and testing. This makes them stand apart from multinationals such as Intel which work on an integrated approach. The Taiwan semiconductor industry consists of 238 IC fabless design companies, 37 packaging and testing companies, 15 fabrication companies, 11 wafer suppliers, 7 substrate suppliers, 3 mask makers and 4 lead frames companies.
Taiwan is the largest wafer foundry supplier, the largest IC packaging and testing services provider and the second largest IC designer. Despite decline in value, the US remains at top position with high market share. Taiwan’s robust infrastructure, skilled workforce,
Government support with relaxed regulatory environment has further aided to its strong technical and competitive edge in global market.
Packaging has always played a critical role in the electronics supply chain. As the physical interface between the processor and the motherboard happen, the package provides a landing zone for a chip’s electrical signals and power supply. With electronics industry transitions to the data-centric era, advanced packaging will play a much larger role than it has in the past.
Packaging is becoming a catalyst for product innovation. Advanced packaging techniques allow integration of diverse computing engines across multiple process technologies with performance parameters similar to a single die, but with a platform scope that far exceeds the die-size limit of single-die integration. These technologies will improve product-level
performance, power and area while enabling a complete rethinking of system architecture.
Samsung’s new innovation is considered one of the most challenging packaging technologies for mass production of high-performance chips, as it requires pinpoint accuracy to vertically interconnect 12 DRAM chips through a three-dimensional configuration of more than 60,000 TSV holes, each of which is one-twentieth the thickness of a single strand of human hair.
The thickness of the package remains the same as current 8-layer High Bandwidth Memory-2 (HBM2) products, which is a substantial advancement in component design. This will help customers release next-generation, high-capacity products with higher performance capacity without having to change their system configuration designs. In addition, the 3D packaging technology also features a shorter data transmission time between chips than the currently existing wire bonding technology, resulting in significantly faster speed and lower power consumption.
Market Stature and Outcome
Semiconductor packaging and assembly technologies are attracting more attention as a driving force to further reduce the cost, enhance the functionality and improve the performance of semiconductor applications without relying on only device scaling. The extreme research in far-field wireless charging technologies coupled with trending Internet of things (IoT) will implement advanced semiconductor packaging inevitable in the
telecommunication industry too.
Semiconductors largely contribute to the global trillion dollar electronics industry. Moreover, the worldwide sales of semiconductors have mounted. The semiconductor market size was valued between $420 billion to $430 billion in 2018, and is estimated to increase with a CAGR of 10-12%, during the forecast period of 2019 to 2025. This data of the industry implies that an ample part of it is attributable to continuous demand influx of the advanced semiconductor packaging market.
As per the reports of Global System for Mobile Communications (GSMA), the number of global IoT connections will increase to billions with increase in global IoT revenue making way for 5G furthermore. With all of these gaining traction, semiconductor packaging is all set to see an extreme upsurge in its revenue in the upcoming years.
Indian Government has also deployed initiatives such as Preferential Market Access (PMS), Electronics Manufacturing Clusters (EMC), and Modified Special Incentive Package Scheme (M-SIPS) in order to achieve a degree of sufficiency in electronics, which will push the semiconductors packaging market beyond boundaries as semiconductor devices are one of the main components of electronic gadgets. Semiconductor packaging and testing are the operations closest to customers in semiconductor manufacturing, and are therefore critical to fulfil demands in the semiconductor market. Although semiconductor packaging consumes considerably less time than wafer fabrication.
Adoption of the Internet as a commercial medium has moved firms to bring innovation in marketing. Since the origin of the e-commerce industry, researchers and developers were working to bring relevant services to easy and cost-effective logistics including efficient packaging. Constant experimentation and improvement is paving way for further fan-out wafer-level packaging, flip-chip, fan-in wafer-level packaging and others. Furthermore, artificial intelligence is enabling tremendous advances in semiconductor technology. With these advancements, the need for latest adaptations is a must so as to get a subtle and confined assembly system.