Synopsys has announced its Verification IP (VIP) and source code test suite for DisplayPort 1.4, featuring DSC 1.2 and for eDP 1.4a/b. The VC VIP, according to the company, allows design teams flexibility to create displays with ease of use and integration.

The VC VIP for DisplayPort 1.4 provides support for high display resolutions. It also features display stream compression (DSC) for lossless low-latency algorithms, increased resolution and colour depths, and reduced power consumption.

Synopsys VIP utilises the SystemVerilog, a UVM-based architecture, to design displays. It comes integrated with the Verdi Protocol Analyzer debug solution and includes debug ports. The VC VIP also features error injection capabilities, built-in-protocol checks, coverage, and verification plans.