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    Packaging 101: Mapping the Semiconductor Packaging Process & Trends

    Back in the day, chip packaging used to be a background activity, but times have changed significantly and there are several reasons for that. 5nm node, 3nm node and 2nm node are currently on the horizon, and researchers and designers have no intentions to stop, in fact, they are aiming for the limitless miniaturization of components. Which in a way might make Moore’s law rather insignificant in the near future. At these remarkably miniaturized nodes, the die becomes very expensive and at the same time, the designer wants to utilize the die as economically as possible while aiming the maximum yields for the chips.

    In account to achieve all these things, some of the major companies are breaking the process, and that’s called chiplets. Chiplets are multiple chips in a package. But when you have multiple chips interconnected in the package, you have to ask how do you package it electrically, thermally, and mechanically? So that explains one of the reasons why packaging is coming to the forefront.

    For the uninitiated, packaging holds a completely different definition in the electronics realm. When talking about packaging, with respect to the electronics spectrum, it is a process that includes the design and production of enclosures for electronic devices ranging from individual semiconductor devices up to complete systems. Electronic packaging is a major discipline within the field so as to develop durable and long-lasting functionaries.

    From the most elementary level consumer and home appliances to the most sophisticated and state-of-the-art machinery and electronic devices, everything functions via a semiconductor, in one way or the other. The Semiconductor packaging process is a standout amongst the most emergent and astoundingly approved sectors. Semiconductor packaging materials are a class of electronic solutions used to form the connection of IC chips to the package substrate.

    Packaging is an essential part of semiconductor manufacturing and design. It affects power, performance, and cost on a macro level, and the basic functionality of all chips on a micro-level.

    Semiconductor packaging has a  crucial role in manufacturing because it is among the closest steps to the end customers.  However,  the complexity of production conditions makes controlling a  semiconductor packaging facility a challenging task, and dynamic factory simulation has been considered as an effective means to fulfil this task.

    Packaging is a backend operation in semiconductor manufacturing. Compared with the frontend operations  (i.e., wafer fabrication and wafer sort),  the backend operations require substantially less time and expenditure.  In addition, the backend operations are closer to the end customers than the frontend operations, marketing time is more critical for the backend operations.

    The global semiconductor packaging market size is expected to reach $60.44 billion by 2030 from $27.10 billion in 2020, growing at a CAGR of 9.10% from 2021 to 2030.

    Semiconductor packaging plays an important role in protecting IC chips from the surrounding environment and ensuring the electrical connection for chip mount on printed wiring boards. High demand for high-speed, high-integration and low power consumption of integrated circuits (ICs) complements the rapid progress of electronics technology such as AI and cloud computing.

    Semiconductor packaging is a supporting case that prevents physical damage and corrosion to silicon wafers, logic units, and memory during the final stage of the semiconductor manufacturing process. It allows the chip to be connected to a circuit board. This packaging involves the grouping of a variety of distinct techniques, which includes 2.5D, 3D packaging, fan-out-wafer-level packaging, and system-in-package. Different ICs have different packaging requirements, thereby providing growth opportunities for the semiconductor packaging market over the traditional packaging process.

    Many types of packages are in use today and more are either in research at universities or ready for production — everything from the complex stacked die with through-silicon via to fan-outs and complex systems-on-chip. Packages come in different materials, can be standard or custom, and can have active or passive cooling.

    Packages used to be considered a fairly non-critical part of the semiconductor design. They are now essential on every level, and there is a race between foundries and OSATs to grab a larger share of this market as complexity and profitability increase.

    In addition, in consumer electronics and industrial products, advanced packaging relies on mechanical engineering principles, such as dynamics, stress analysis, heat transfer, and fluid mechanics, and protects components from mechanical damage, cooling, RF noise emission, and electrostatic discharge. Thus, to improve the performance, reliability, and cost-effectiveness of electronics systems, advanced packaging technology is being used for the packaging of semiconductors.

    With the rapid growth in semiconductor packaging market revenue, specifically fan-out wafer-level packaging along with an increase in demand for smartphones, devices, and Internet of Things (IoT), semiconductor packaging suppliers are developing processes and ways to reduce the overall cost of advanced packaging and provide maximum operational efficiency. In recent times, it is mainly used for high-end products and for applications related to niche-market, such as wafer and die production, due to its high cost in its operation.

    To understand better the semiconductor packaging challenges, processes and the future trends that are being anticipated, ELE Times Sub Editor and Technology Correspondent Mayank Vashisht Had a candid chat with Steve Roberts, Innovation Manager of RECOM Power


    Steve Roberts, Innovation Manager of RECOM Power

    ELE Times: Back in the day, chip packaging was an afterthought. Chipmakers were more worried about IC design. Packaging was considered a mere commodity, which was simply used to house the design. What has changed over the years?

    As both the supply voltage and the power density has increased, the chip packaging is now considered to be an integral part of the design and not just an “add on” to make handling or labelling easier. For power electronics, getting the heat efficiently out from the semiconductor junction to the surroundings is essential if the full electrical performance of the chip is to be realised. For automotive or electric vehicle (EV) applications, the onboard low voltage supply voltage is now commonly 48 VDC with 60 VDC or 100VDC transients which means that the packaging must also withstand these voltages, even in dirty, corrosive or humid environments.

    ELE Times: How efficient are the advanced forms of heterogeneous integration, which involves 2.5D/3D, fan-out and system-in-package in comparison to the traditional ways of packaging?

    It is not just the power density that has increased, but also the chip complexity. In order to pack ever more connections and functionality into the same size, 3D packaging is often the only practical solution. Again, EV applications are one of the driving forces behind these packaging innovations, as artificial intelligence, LIDAR and image processing are becoming mainstream elements in self-driving or driver-assistance systems.

    ELE Times: Advanced packaging tends to grab the headlines and is making inroads. Yet, wire-bond and flip-chip are still widely used today. Your thoughts

    Flip-chip is still a very efficient packaging system for power electronics – the direct connection with the copper lead frame is a low impedance solution both electrically and thermally. Wire bonding is also still useful for mixed-signal packaging where two or more different chips are placed in the same package, one handling the low power signal routing, the other the higher power side. Often, wire bonding is the only practical connection technology when the dies are very different sizes and shapes.

    ELE Times: What are the new areas that packaging houses are fishing for their growth?

    The keyword here is ‘embedding’. Not only are inter-chip connections being embedded inside the packaging by stacking the dies, but also chips are being embedded inside the PCB substrate. All of these techniques reduce the length of the interconnections which improves the bandwidth, reduces latency and lowers the EMI.

    ELE Times: What is the way forward in terms of innovation for packaging technologies?

    I think that most of the innovations will be in the production processes, reducing cost and improving yield, rather than any novel packaging techniques.

    ELE Times: Please enlist some of the future packaging trends from your vantage point.

    There is still much more R&D needed to find solutions for packaging very dissimilar materials, such as IC chips and ferrites. As a manufacturer of DC/DC switching regulators, embedding power inductors are an important part of our 3DPP (3D power packaging) strategy. On the long-term horizon, we also need to find solutions that will allow our products to be more easily disassembled at the end of their useful life to allow improved recycling or reuse. This is a very difficult problem to solve, but one where we will eventually need a solution.

    Mayank Vashisht | Sub Editor | ELE Times

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