Anritsu Corporation (President Hirokazu Hamada) is pleased to announce the sales launch of its Signal Quality Analyzer-R MP1900A series with upgraded PCI Express 5.0*1 Receiver and USB 3.2 x2-lane Test functions.
These PCI 5.0 CEM*2-function upgrades provide an effective Sequence Editor for debugging Link Training*3 as well as an optional accessory for compensating return path loss. Additionally, the USB 3.2 x2-lane measurement specified by the new standard for USB Type-C connectors*4 is also supported as a software option.
The all-in-one MP1900A supporting both PCI Express and USB standards helps resolve the measurement challenges of these new standards while contributing to customers’ evaluation efficiency and making the best use of their investment in test equipment.
The rollout of commercial 5G services supports high-speed communications using large data to facilitate rapid advances in the latest technologies, including IoT and AI. At the same time, the interfaces of transmission equipment, such as servers and storage, in data centers forming the backbone of this technology revolution are being upgraded to PCI Express for faster transmission of larger data traffic. Evaluation of PCI Express 5.0 is challenging, especially when there are problems with transitioning to the DUT test mode at Link Training. Moreover, BER measurements at Compliance Tests*5 may be impossible when the return path loss is large.
In addition, the standard for USB Type-C connectors built into various digital equipment, such as smartphones, tablet PCs, etc., as interfaces for high-speed transmission of large video and data files has been upgraded to USB 3.2 supporting 10 Gbit/s x 2 lanes, which increases test challenges, such as the time required to measure two lanes compared to earlier 1-lane measurements.
The MP1900A is a high-performance BERT*6 supporting Receiver Tests of high-speed computer and data communications interfaces, such as PCIe, USB, Thunderbolt, 400 and 800GbE, etc.
As well as a dedicated GUI optimized for debugging PCI Express 5.0 Link Training challenges, an optional software Sequence Editor function has also been developed. When the PCI Express 5.0 Compliance Test DUT return channel path loss is large, the BER can still be measured by using the accessory Re-Driver Set to compensate for loss.
In addition, the USB 3.2 Gen1/Gen2 x1/x2-lane DUT Receiver Test is supported by using the BERT 2ch options with the USB 3.2 x2 Link Training software option for lane identification using two-way Link Training and BER measurement after transitioning to the test mode, which can be fully automated using GRL’s automation software.
- PCIe, USB, Thunderbolt Receiver Test Solution Pages
Resolves PCIe Gen5 receiver test challenges
- For debugging Link Training using PCIe5.0-dedicated Sequence Editor function
- For DUT Receiver Test with return channel path losses of up to 24 dB (typ.) using external accessory Re-Driver Set
Supports USB 3.2 x1/x2-lane measurement
- Unlike conventional USB 3.2 x1-lane measurement, supports x2-lane measurement using USB 3.2 x2 Link Training software option (requires PPG and ED 2ch options)
Cuts test equipment investment costs and reduce test workloads
- Hardware support from 2.4 to 21 Gbit/s (USB 3.2) with extended support to 32.1 Gbit/s (PCIe 5.0) in software
- Software for automating measurement procedure supports real-time oscilloscopes from major manufacturers.*
*Contact our sales representative for details about supported oscilloscopes.
About Granite River Labs
Granite River Labs (GRL) offers various engineering services and test solutions to customers using high-speed interface technologies. GRL provides ideal test solutions based on the company’s strong cooperative relationship with world-leading businesses for applications ranging from test fixtures to instruments for measuring ultra-high-speed signals by combining high-level test equipment, technical know-how, and automation software.
[Target Markets and Applications]
- Target Markets: High-end servers, high-performance computers, communications equipment
- Applications: R&D into high-speed electronic devices, chipsets, memory cards, graphics cards, etc.
[*1] PCI Express
One bus standard for connecting computers and peripheral equipment; standardized as Gen1 to Gen5 depending on transmission speed.
Abbreviation for Card Electromechanical; PCI-SIG standard regulating electrical and mechanical specifications for cards and motherboards.
[*3] Link Training
Synchronization process to establish a link between connected equipment with interfaces meeting the PCI and USB standards.
[*4] USB Type-C® Connector
Registered trademark of USB Implementers Forum for reversible 24-pin connector developed in 2014.
[*5] Compliance Test
Certification test using pass/fail evaluation standards defined by PCI-SIG.
Abbreviation for Bit Error Rate Tester; test instrument for measuring a digital-signal error rate.
For more information, visit www.anritsu.com